View MIC2184BQS_677098.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MIC2184
Micrel
MIC2184
Low Voltage Buck PWM Control IC Final Information
General Description
Micrel's MIC2184 is a high efficiency PWM buck control IC. With its wide input voltage range of 2.9V to 14V, the MIC2184 can be used to efficiently step voltages down in 1- or 2-cell Li Ion battery powered applications, as well as in fixed 3.3V, 5V, or 12V systems. Efficiencies over 90% are achievable over a wide range of load conditions with the MIC2184's PWM control scheme. The operating frequency can be divided by two by raising the FREQ/2 pin to VDD. This allows the user to optimize efficiency versus board space. It also allows the MIC2184 to be externally synchronized to frequencies below its nominal 400KHz. The MIC2184 features an oscillator output, FreqOut, which can be used to implement a simple charge pump in low voltage applications. The output of the charge pump can be fed into the gate drive power circuitry via the VINP pin, allowing enhanced gate drive, hence higher efficiencies, despite low input voltages. MIC2184 features a 1A shutdown mode, and a programmable undervoltage lockout, making it well suited for portable applications. The MIC2184 is available in 16 pin SOP and QSOP package options with a junction temperture range range from -40C to +125C.
Features
* * * * * * * * * * * * * * * * * * * * * * Input voltage range: 2.9V to 14V >90% efficiency Oscillator frequency of 400kHz Frequency divide-by-two pin Frequency sync to 600kHz FrequOut oscillator output allows simple charge pump implementation in low voltage systems 1.245V reference output Front edge blanking 5 output driver Soft start PWM current mode control 1A shutdown current Cycle-by-cycle current limiting Frequency foldback short circuit protection Adjustable under-voltage lockout 16 pin narrow-body SOIC and QSOP package options 3.3V to 2.5V/1.8V/1.5V conversion DC power distribution systems Wireless Modems ADSL line cards 1-and 2-cell Li Ion battery operated equipment Satellite Phones
Applications
Typical Application
VIN = 3.3V
16
120F (x2) 6.3V
VINP
1 7 2 16 10 4 3 13
15m CSH CSL OUTP
9 8
MIC2184 EFFICIENCY
100 95 90
VINA EN/UVLO FreqOut FREQ/2 VDD COMP SS VREF SYNC
11
EFFICIENCY (%)
14
Q3 Si9803DY(x2) 4.7H
MIC2184
VOUT 2.5V @5A
85 80 75 70 65 60 55 50 0
PGND FB SGND
5
12 6
220F(x2) 6.3V
VIN = 3.3V VOUT = 2.5V fS = 200kHz
1 2 3 4 OUTPUT CURRENT (A) 5
Adjustable Output Buck Converter
Micrel, Inc. * 1849 Fortune Drive * San Jose, CA 95131 * USA * tel + 1 (408) 944-0800 * fax + 1 (408) 944-0970 * http://www.micrel.com
December 10, 2001
1
MIC2184
MIC2184
Micrel
Ordering Information
Part Number MIC2184BM MIC2184BQS Output Voltage Adjustable Adjustable Frequency 400KHz 400KHz Junction Temp. Range -40C to +125C -40C to +125C Package 16-lead SOP 16-lead QSOP
Pin Configuration
VINA 1 FreqOut 2 SS 3 COMP 4 SGND 5 FB 6 EN/UVLO 7 CSL 8 16 VINP 15 FREQ/2 14 OUTP 13 VREF 12 PGND 11 SYNC 10 VDD 9 CSH
16 Lead SOIC (M)
MIC2184
2
December 10, 2001
MIC2184
Micrel
Pin Description
Pin Number 1 Pin Name VINA Pin Function Analog voltage input voltage to the circuit. This powers up the analog sections of the die and does not need to be the same voltage as Pin 16 (VINP). This provides a digital signal output signal at half the switching frequency. This signal swings from 0 to 3V, and can be used to drive an external capacitive doubler to provide a higher voltage to the VINP input. Soft start reduces the inrush current and delays and slows the output voltage rise time. A 5A current source will charge the capacitor up to VDD. A 1F capacitor will soft start the switching regulator in 1.5ms. Compensation (Output): Internal error amplifier output. Connect to a capacitor or series RC network to compensate the regulator's control loop. Small signal ground: must be routed separately from other grounds to the (-) terminal of COUT. Feedback Input - the circuit regulates this pin to 1.245V. Enable/UnderVoltage Lockout (input): A low level on this pin will power down the device, reducing the quiescent current to under 5uA. This pin has two separate thresholds, below 1.5V the output switching is disabled, and below 0.9V the part is forced into a complete micropower shutdown. The 1.5V threshold functions as an accurate undervoltage lockout (UVLO) with 140mV hysteresis. The (-) input to the current limit comparator. A built in offset of 100mV between CSH and CSL in conjunction with the current sense resistor sets the current limit threshold level. This is also the (-) input to the current amplifier. The (+) input to the current limit comparator. A built in offset of 100mV between CSH and CSL in conjunction with the current sense resistor sets the current limit threshold level. This is also the (+) input to the current amplifier. 3V internal linear-regulator output. VDD is also the supply voltage bus for the chip. Bypass to SGND with 1F. Frequency Synchronization (Input): Connect an external clock signal to synchronize the oscillator. Leading edge of signal above 1.5V starts the switching cycle. Connect to SGND if not used. MOSFET driver power ground, connects to source of synchronous MOSFET and the (-) terminal of CIN. The 1.245V voltage reference is available on this pin. A 0.1F capacitor should be connected from this pin to ground. High current drive for high side P channel MOSFET. Voltage swing is from ground to VINP. On-resistance is typically 2.5. When this is low, the oscillator frequency is 400KHz. When this pin is raised to VDD, the oscillator frequency is 200KHz. Power Input voltage to the circuit. The output gate drivers are powered from this supply. The current sense resistor RCS should be connected as close as possible to this pin.
2
FreqOut
3
SS
4 5 6 7
COMP SGND FB EN/UVLO
8
CSL
9
CSH
10 11
VDD SYNC
12 13 14 15 16
PGND VREF OUTP FREQ/2 VINP
December 10, 2001
3
MIC2184
MIC2184
Micrel
Absolute Maximum Ratings (Note 1)
Supply Voltage (VINA, VINP) ......................................... 15V Digital Supply Voltage (VDD) ........................................... 7V Comp Pin Voltage (VCOMP) ............................ -0.3V to +3V Feedback Pin Voltage (VFB) .......................... -0.3V to +3V Enable Pin Voltage (VEN/UVLO) ..................... -0.3V to 15V Current Sense Voltage (VCSH-VCSL) ............... -0.3V to 1V Sync Pin Voltage (VSYNC) ................................ -0.3V to 7V Freq/2 Pin Voltage (VFREQ/2) ............................ -0.3V to 7V Power Dissipation (PD) 16 lead SOIC ................................. 400mW @ TA = 85C 16 lead QSOP ............................... 245mW @ TA = 80C Ambient Storage Temp ............................ -65C to +150C ESD Rating, ............................................................. Note 3
Operating Ratings (Note 2)
Supply Voltage (VINA, VINP) ........................ +2.9V to +14V Ambient Operating Temperature ......... -40C TA +85C Junction Temperature ....................... -40C TJ +125C Output Voltage Range ...................................... 1.3V to 12V PackageThermal Resistance JA 16-lead SOP ............................................... 100C/W JA 16-lead QSOP ............................................. 163C/W
Electrical Characteristics
VINA = VINP = VCSH = 5V, VOUT = 3.3V, VEN/UVLO = 5V, VFREQ/2 = 0V, TJ = 25C, unless otherwise specified. Bold values indicate -40C < TJ < +125C. Parameter Regulation Feedback Voltage Reference (1%) (2%) Feedback Bias Current Output Voltage Line Regulation Output Voltage Load Regulation Output Voltage Total Regulation Input & VDD Supply VINA Input Current VINP Input Current, Note 4 Shutdown Quiescent Current Digital Supply Voltage (VDD) Digital Supply load regulation Undervoltage Lockout UVLO Hysteresis Reference Output(VREF) Reference Voltage (1.5%) (2.5%) Reference Voltage Line Regulation Reference Voltage Load Regulation Enable/UVLO Enable Input Threshold UVLO Threshold UVLO Hysteresis Enable Input Current VEN/UVLO = 5V (Turn-on threshold) 0.6 1.4 0.9 1.5 140 0.2 5 1.2 1.6 V V mV A 5V < VINA < 12V 0 < IREF < 100A 1.226 1.213 2 1 1.245 1.264 1.276 V V mV mV (Excluding external MOSFET gate current) VEN/UVLO = 0V; (IVINA + IVINP) IL = 0 IL = 0 to 1mA VDD upper threshold (turn on threshold) 2.82 0.7 1.0 0.5 3.0 0.03 2.75 100 5 3.18 mA mA A V V V mV 5V VIN 12V 0mV < (VCSH - VCSL) < 75mV 5V VINA 12V, 0mV < (VCSH - VCSL) < 75mV (3%) 1.208 1.233 1.22 50 0.04 0.9 1.282 1.245 1.257 1.27 V V nA %/V % V Condition Min Typ Max Units
MIC2184
4
December 10, 2001
MIC2184
Parameter Soft Start Soft Start Current Current Limit Current Limit Threshold Voltage Error Amplifier Error Amplifier Gain Current Amplifier Current Amplifier Gain Oscillator Section Oscillator Frequency (fO) Maximum Duty Cycle Minimum On Time Freq/2 Frequency (fO) Frequency Foldback Threshold Frequency Foldback Frequency SYNC Threshold Level SYNC Input Current SYNC Minimum Pulse Width SYNC Capture Range FreqOut Output FreqOut Frequency FreqOut Current Drive Note 6 Sink Source Gate Drivers Rise/Fall Time Output Driver Impedance CL = 3300pF Source; VINP = 12V Sink; VINP = 12V Source; VINP = 5V Sink; VINP = 5V
Note 1:
Micrel
Condiion Min Typ Max Units A
5
Voltage on CSH-CSL to trip current limit
100
mV
20
V/V
3.0
V/V
360 VFB = 1.0V VFB = 1.5V VFREQ/2 = 5V Measured on FB 170 100
400
440
kHz %
185 200 0.3 90 0.6 1.4 0.1 200 2.2 5 230
ns kHz V kHz V A ns 600 kHz
Note 5
fO +15 % fO / 2 8 -6
kHz mA mA
50 1.8 1.6 2.6 2.4 4 3.5
ns
Absolute maximum ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply when operating the device outside of its operating ratings. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(Max), the junction-to-ambient thermal resistance, JA, and the ambient temperature, TA. The device is not guaranteed to function outside its operating rating. Devices are ESD sensitive. Handling precautions recommended. See application information for I(VINP) vs. VINP. See application information for limitations on maximum operating frequency. The frequency on FreqOut is half the frequency of the oscillator, or half the frequency of the external Sync signal.
Note 2. Note 3. Note 4: Note 5: Note 6:
December 10, 2001
5
MIC2184
MIC2184
Micrel
Typical Characteristics
Quiescent Current vs. Input Voltage
4.5 QUIESCENT CURRENT (mA) 4 3.5 3 2.5 2 1.5 1 0.5 0 0 ISTANDBY 5 10 INPUT VOLTAGE (V) 15 200kHz IQ = IVINA + IVINP
QUIESCENT CURRENT (mA)
Quiescent Current vs. Temperature
1.4 1.2 1.0 0.8 0.6 0.4 IQ = IVINA + IVINP 0.2 V A = V P = 3.3V IN IN 0 -40 -20 0 20 40 60 80 100120140 TEMPERATURE (C) 400kHz 200kHz ISTANDBY
VDD (V)
400kHz
3.10 3.05 3.00 2.95 2.90 2.85 2.80 0
VDD vs. Input Voltage
VINA = VINP
5 10 INPUT VOLTAGE (V)
15
3.005 3.000 2.995 VDD (V) 2.990 2.985 2.980 2.975 2.970 0
VDD vs. Load
3.08 3.06
VDD vs. Temperature
REFERENCE VOLTAGE (V)
Error Amp Reference Voltage vs. Input Voltage
1.2451 1.2449 1.2447 1.2445 1.2443 1.2441 0 2 4 6 8 10 12 14 INPUT VOLTAGE (V)
VINA = VINP = 5V
VDD (V)
3.04 3.02 3.00 2.98 2.96 2.94 VIN = 5V
0.2 0.4 0.6 0.8 1 1.2 VDD LOAD CURRENT (mA)
2.92 -40 -20 0 20 40 60 80 100120140 TEMPERATURE (C)
Error Amp Reference Voltage vs. Temperature
1.246 FREQUENCY VARIATION (%) 2 1.5 1 0.5 0 -0.5 -1 -1.5 -2 0
Frequency Variation vs. Input Voltage
5 200kHz SOFT START CURRENT (A) 3 1 -1 -3 -5 -7 -9 -11
Frequency Variation vs. Temperature
200kHz 400kHz
REFERENCE VOLTAGE (V)
1.245 1.244 1.243 1.242 1.241 VIN = 3.3V 1.24 -40 -20 0 20 40 60 80 100120140 TEMPERATURE (C)
400kHz
2
4 6 8 10 12 INPUT VOLTAGE (V)
14
-13 -15 -50 -30 -10 10 30 50 70 90 110 TEMPERATURE (C)
Soft Start Current vs. Temperature
102.0 4.9 100.0 THRESHOLD (mV)
Overcurrent Threshold vs. Input Voltage
102 101 THRESHOLD (mV) 100 99 98 97 96 2 4 6 8 10 12 14 INPUT VOLTAGE (V)
Overcurrent Threshold vs. Temperature
VIN = 3.3V
CURRENT (A)
4.8 4.7 4.6 4.5 4.4 -40 -20 0 20 40 60 80 100120140 TEMPERATURE (C)
98.0 96.0 94.0 92.0 90.0 0
95 -40 -20 0 20 40 60 80 100120140 TEMPERATURE (C)
MIC2184
6
December 10, 2001
MIC2184
Micrel
OUTP Drive Impedance vs. Input Voltage
4 3.5 IMPEDANCE () 3 2.5 2 1.5 1 0 SINK SOURCE 5 10 INPUT VOLTAGE (V) 15
December 10, 2001
7
MIC2184
MIC2184
Micrel
Functional Diagram
VIN CIN CDECOUP
VINA
1
VREF 1.245V
OVERCURRENT COMPARATOR 0.1V
9
CSH RSENSE
EN/UVLO VDD
7
BIAS
10 VDD
GAIN 3.7
8
CSL VINP
ON
CURRENT SENSE AMP
16
fs/4 CONTROL SYNC FREQ/2 FreqOut
11
14
OUTP Q1 L1 VOUT D1 COUT
15
OSC /2
RESET SLOPE COMPENSATION 12
PGND
2
PWM COMPARATOR SS COMP
3
gm = 0.0002 VREF gain = 20 ERROR AMP 100k
4
6
FB
0.3V fs/4 VREF
13
VREF FREQUENCY FOLDBACK
5
SGND
Figure 1. MIC2184 Block Diagram
Functional Characteristics
Controller Overview and Functional Description The MIC2184 is a BiCMOS, switched mode, synchronous, step down (buck) converter controller. It uses a P-Channel MOSFET, which allows the controller to operate at 100% duty cycle and eliminates the need for a high side drive bootstrap circuit. Current mode control is used to achieve superior transient line and load regulation. An internal corrective ramp provides slope compensation for stable operation above a 50% duty cycle. The controller is optimized for high efficiency, high performance DC-DC converter applications. Figure 1 is a block diagram of the MIC2184 configured as a synchronous buck converter. At the beginning of the switching cycle, the OUTP pin pulls low and turns on the high-side MIC2184 8
P-Channel MOSFET, Q1. Current flows from the input to the output through the current sense resistor, MOSFET and inductor. The current amplitude increases, controlled by the inductor. The voltage developed across the current sense resistor, RSENSE, is amplified inside the MIC2184 and combined with an internal ramp for stability. This signal is compared to the output of the error amplifier. When the current signal equals the error voltage signal, the P-channel MOSFET is turned off. The inductor current flows through the diode, D1. At the beginning of the next switching cycle, the P-channel MOSFET is turned on which turns off the diode, D1.
December 10, 2001
MIC2184
The MIC2184 controller is broken down into 7 functions. * Control loop * PWM operation * Current mode control * Current limit * Reference, enable and UVLO * FreqOut * MOSFET gate drive * Oscillator and Sync * Soft-start Control Loop
PWM Control Loop
Micrel
Current Limit The output current is detected by the voltage drop across the external current sense resistor (RSENSE in Figure 1.). The current sense resistor must be sized using the minimum current limit threshold. The external components must be designed to withstand the maximum current limit. The current sense resistor value is calculated by the equation below:
RSENSE = MIN _ CURRENT _ SENSE _ THRESHOLD IOUT _ MAX
The maximum output current is:
IOUT _ MAX = MAX _ CURRENT _ SENSE _ THRESHOLD RSENSE
The MIC2184 uses current mode control to regulate the output voltage. This dual control loop method (illustrated in Figure 2) senses the output voltage (outer loop) and the inductor current (inner loop). It uses inductor current and output voltage to determine the duty cycle of the buck converter. Sampling the inductor current effectively removes the inductor from the control loop, which simplifies compensation.
VIN Switching Converter VOUT
Voltage Divider IINDUCTOR Switch Driver VERROR VREF
IINDUCTOR
VERROR
tON tPER D = tON/tPER
Figure 2. Current Mode Control Example As shown in Figure 1, the inductor current is sensed by measuring the voltage across the resistor, RSENSE. A ramp is added to the amplified current sense signal to provide slope compensation, which is required to prevent unstable operation at duty cycles greater than 50%. A transconductance amplifier is used for the error amplifier, which compares an attenuated sample of the output voltage with a reference voltage. The output of the error amplifier is the compensation pin (Comp), which is compared to the current sense waveform in the PWM block. When the current signal becomes greater than the error signal, the comparator turns off the high side drive. The COMP pin provides access to the output of the error amplifier and allows the use of external components to stabilize the voltage loop. December 10, 2001 9
The current sense pins CSH (pin 9) and CSL (pin 8) are noise sensitive due to the low signal level and high input impedance. The PCB traces should be short and routed close to each other. A small (1nF) capacitor across the pins will attenuate high frequency switching noise. When the peak inductor current exceeds the current limit threshold, the overcurrent comparator turns off the high side MOSFET for the remainder of the switching cycle, effectively decreasing the duty cycle. The output voltage drops as additional load current is pulled from the converter. When the voltage at the feedback pin (FB) reaches approximately 0.3V, the circuit enters frequency foldback mode and the oscillator frequency will drop to 1/4 of the switching frequency. This limits the maximum output power delivered to the load under a short circuit condition. Reference, Enable and UVLO Circuits The output drivers are enabled when the following conditions are satisfied: * The VDD voltage (pin 10) is greater than its undervoltage threshold. * The voltage on the enable pin (pin 7) is greater than the enable UVLO threshold. The enable pin (pin 7) has two threshold levels, allowing the MIC2184 to shut down in a low current mode, or turn off output switching in standby mode. An enable pin voltage lower than the shutdown threshold turns off all the internal circuitry and places the MIC2184 in a micropower shutdown mode. If the enable pin voltage is between the shutdown and standby thresholds, the internal bias, VDD and reference voltages are turned on. The soft start pin is forced low by an internal discharge MOSFET. The output drivers are inhibited from switching. The OUTP pin is in a high state and the OUTN pin remains in a low state. Raising the enable voltage above the standby threshold allows the soft start capacitor to charge and enables the output drivers. The standby threshold is specified in the electrical characteristics. A resistor divider can be used with the enable pin to prevent the power supply from turning on until a specified input voltage is reached. The circuit in Figure 3 shows how to connect the resistors.
MIC2184
MIC2184
MIC2184 VIN 1.5V Typical
Micrel
supply. The VINP pin and CSH pin must be connected to the same potential. MOSFET Selection The P-channel MOSFET must have a VGS threshold voltage equal to or lower than the input voltage when used in a buck converter topology. There is a limit to the maximum gate charge the MIC2184 will drive. Higher gate charge MOSFET will slow down the turn-on and turn-off time of the MOSFET. Slower transition times will cause higher power dissipation in the MOSFET due to higher switching transition losses. The MOSFET gate charge is also limited by power dissipation in the MIC2184. The power dissipated by the gate drive circuitry is calculated below: PGATE_DRIVE = Q GATE x VINP x fS where: Qgate is the total gate charge of both the N and Pchannel MOSFETs. fS is the switching frequency VINP is the gate drive voltage at the VINP pin The graph in Figure 4 shows the total gate charge that can be driven by the MIC2184 over the input voltage range, for different values of switching frequency.
Frequency vs. Max. Gate Charge
200x10-9
TOTAL GATE CHARGE (C)
R1
Bias Circuitry EN/UVLO (7) 140mV Hysteresis (typical)
R2
Figure 3. UVLO Circuitry The line voltage turn on trip point is: VINPUT _ ENABLE = VTHRESHOLD x R2 R1 + R2
where: VTHRESHOLD is the voltage level of the internal comparator reference, typically 1.5V The input voltage hysteresis is equal to: VINPUT _ HYST = VHYST x R1 + R2 R2
where: VHYST is the internal comparator hysteresis level, typically 140mV. VINPUT_HYST is the hysteresis at the input voltage The MIC2184 will be disabled when the input voltage drops back down to: VINPUT_OFF = VINPUT_ENABLE - VINPUT_HYST = R2 R1 + R2 Either of 2 UVLO conditions will pull the soft start capacitor low. * When the VDD voltage drops below its undervoltage lockout level. * When the enable pin drops below the its enable threshold The internal bias circuit generates an internal 1.245V bandgap reference voltage for the voltage error amplifier and a 3V VDD voltage for the internal control circuitry. The VREF pin (pin 13) should be decoupled with a 0.1f capacitor placed close to the pin. The VDD pin must be decoupled with a 1F ceramic capacitor. The capacitor must be placed close to the VDD pin. The other end of the capacitor must be connected directly to the ground plane. MOSFET Gate Drive The MIC2184 is designed to drive a high side P-channel MOSFET. The source pin of the P-channel MOSFET is connected to the input of the power supply. It is turned on when OUTP pulls the gate of the MOSFET low. The advantage of using a P-channel MOSFET is that it does not require a bootstrap circuit to boost the gate voltage higher than the input, as would be required for an N-channel MOSFET. The VINP pin (pin 16) supplies the drive voltage to the gate drive pin, OUTP. VINP pin is usually connected to the input (VTHRESHOLD - VHYST) x MIC2184 10
180x10-9 160x10-9 140x10-9 120x10-9 100x10-9 80x10-9 500kHz 60x10-9 40x10-9 20x10-9 0x100 3 5 7 9 11 13 15 17 INPUT VOLTAGE (V) 600kHz 200kHz 300kHz 400kHz
Figure 4. MIC2184 Frequency vs Max. Gate Charge Oscillator & Sync The internal oscillator is free running and requires no external components. The f/2 pin allows the user to select from two switching frequencies. A low level set the oscillator frequency to 400kHz and a high level set the oscillator frequency to 200kHz. The maximum duty cycle for both frequencies is 100%. This is another advantage of using a P-channel MOSFET for the high-side drive; it can continuously turned on. A frequency foldback mode is enabled if the voltage on the feedback pin (pin 6) is less than 0.3V. In frequency foldback, the oscillator frequency is reduced by approximately a factor of 4. Frequency foldback is used to limit the energy delivered to the output during a short circuit fault condition. The SYNC input (pin 11) lets the MIC2184 synchronize with an external clock signal. The rising edge of the sync signal generates a reset signal in the oscillator, which turns off the low side gate drive output. The high side drive then turns on, restarting the switching cycle. The sync signal is inhibited when the controller operates in frequency foldback. The sync signal frequency must be greater than the maximum speciDecember 10, 2001
MIC2184
fied free running frequency of the MIC2184. If the synchronizing frequency is lower, double pulsing of the gate drive outputs will occur. When not used, the sync pin must be connected to ground. The maximum recommended output switching frequency is 600kHz. Synchronizing to higher frequencies may be possible, however, higher power dissipation in the internal gate drive circuits will occur. The MOSFET gates require charge to turn on the device. The average current required by the MOSFET gate increases with switching frequency. Soft Start Soft start reduces the power supply input surge current at start up by controlling the output voltage risetime. The input surge appears while the output capacitance is charged up. A slower output risetime will draw a lower input surge current. Soft start may also be used for power supply sequencing. The soft start voltage is applied directly to the PWM comparator. A 5A internal current source is used to charge up the soft start capacitor. The capacitor is discharged when either the enable pin voltage drops below the standby threshold or the VDD voltage drops below its UVLO level. The part switches at a low duty cycle when the soft start pin voltage is zero. As the soft start voltage rises from 0V to 0.7V, the duty cycle increases from the minimum duty cycle to the operating duty cycle. The oscillator runs at the foldback frequency (1/4 of the switching frequency) until the feedback voltage rises above 0.3V. The risetime of the output is dependent of the soft start capacitor output capacitance, input and output voltage and load current. Voltage Setting Components The MIC2184 requires two resistors to set the output voltage as shown in Figure 5.
MIC2184 Voltage Amplifier Pin 6 R2 VREF 1.245V VOUT
Micrel
Efficiency Considerations Efficiency is the ratio of output power to input power. The difference is dissipated as heat in the buck converter. Under light output load, the significant contributors are: * The VINA supply current * The VINP supply current, which includes the current required to switch the external MOSFET * Core losses in the output inductor To maximize efficiency at light loads: * Use a low gate charge MOSFET or use the smallest MOSFET, which is still adequate for maximum output current. * Use a ferrite material for the inductor core, which has less core loss than an MPP or iron power core. Under heavy output loads the significant contributors to power loss are (in approximate order of magnitude): * Resistive on time losses in the MOSFET * Switching transition losses in the MOSFET * Inductor resistive losses * Current sense resistor losses * Input capacitor resistive losses (due to the capacitors ESR) To minimize power loss under heavy loads: * Use low on resistance MOSFETs. Use low threshold logic level MOSFETs when the input voltage is below 5V. Multiplying the gate charge by the on resistance gives a figure of merit, providing a good balance between low load and high load efficiency. * Slow transition times and oscillations on the voltage and current waveforms dissipate more power during the turn on and turn off of the MOSFET. A clean layout will minimize parasitic inductance and capaci tance in the gate drive and high current paths. This will allow the fastest transition times and waveforms without oscillations. Low gate charge MOSFETs will transition faster than those with higher gate charge requirements. * For the same size inductor, a lower value will have fewer turns and therefore, lower winding resistance. However, using too small of a value will require more output capacitors to filter the output ripple, which will force a smaller bandwidth, slower transient response and possible instability under certain conditions. * Lowering the current sense resistor value will de crease the power dissipated in the resistor. However, it will also increase the overcurrent limit and will require larger MOSFETs and inductor components. * Use low ESR input capacitors to minimize the power dissipated in the capacitors ESR.
R1
Figure 5 The output voltage is determined by the equation below. R1 R2 Where: VREF for the MIC2184 is typically 1.245V. Lower values of R1 are preferred to prevent noise from appearing on the FB pin. A typically recommended value is 10k. If R1 is too small in value it will decrease the efficiency of the power supply, especially at low output loads. Once R1 is selected, R2 can be calculated with the following formula. VOUT = VREF x 1 + R2= VREF x R1 VOUT - VREF 11
December 10, 2001
MIC2184
MIC2184
Micrel
Package Information
PIN 1
0.157 (3.99) 0.150 (3.81)
DIMENSIONS: INCHES (MM)
0.020 (0.51) REF 0.050 (1.27) BSC
0.020 (0.51) 0.013 (0.33) 0.0098 (0.249) 0.0040 (0.102)
45 0-8 0.050 (1.27) 0.016 (0.40) 0.244 (6.20) 0.228 (5.79)
0.0648 (1.646) 0.0434 (1.102)
0.394 (10.00) 0.386 (9.80)
SEATING PLANE
16-Pin SOP (M)
PIN 1
0.157 (3.99) 0.150 (3.81)
DIMENSIONS: INCHES (MM)
0.009 (0.2286) REF 0.025 (0.635) BSC 0.0098 (0.249) 0.0040 (0.102)
0.012 (0.30) 0.008 (0.20)
0.0098 (0.249) 0.0075 (0.190)
45
8 0
SEATING 0.0688 (1.748) PLANE 0.0532 (1.351)
0.196 (4.98) 0.189 (4.80)
0.050 (1.27) 0.016 (0.40) 0.2284 (5.801) 0.2240 (5.690)
16-Pin QSOP (QS)
MICREL INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131
TEL
USA
+ 1 (408) 944-0800
FAX
+ 1 (408) 944-0970
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2001 Micrel Incorporated
MIC2184
12
December 10, 2001

▲Up To Search▲

Price & Availability of MIC2184BQS

	To Download MIC2184BQS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .